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    • 专利摘要:
    LAMINATED BUS FOR POWER CONVERTER AND CONVERTER OF THE SAME This patent application describes a laminated bus arrangement for use in a three-level power converter and a power converter. The laminated bus arrangement comprises a first bus layer comprising a neutral point sub bus configured to make electrical connections between the respective components in the three-level power converter and a neutral point potential, a second bus layer comprising a plurality of sub-buses configured to make electrical connections between the respective components in the three-level power converter and a positive direct current (DC) input, a negative DC input and an alternating current (AC) input / output in the power converter levels, and between respective semiconductor switching components. The present application can effectively reduce stray inductance.
    公开号:BR102013027196B1
    申请号:R102013027196-9
    申请日:2013-10-22
    公开日:2020-12-29
    发明作者:Yan Li；Hongjian Gan；Senlin Wen；Jianping Ying
    申请人:Delta Electronics, Inc；
    IPC主号:
    专利说明:

    This application claims priority to Chinese Patent Application No. 201210403971.1, filed on October 22, 5, 2012, all content of which is incorporated herein by reference. - TECHNICAL FIELD í
    The present application relates to a laminated bus, and, in particular, to a bus structure. laminate 10 with two layers of busbars and a three-level power converter NPC (neutral point hitch) with the laminate bus. FUNDAMENTALS. ;
    Currently, variable frequency converters are widely used in industry fields and tend to be developed for high voltage, high current, high power density, high reliability and low cost. In the high voltage variable frequency field, since the power converter is limited by the performance of 20 semiconductor components, a three-level NPC topology is generally used. |
    Figure 1 is a circuit diagram showing a circuit phase of a typical three-level NPC topology. Although Figure 1 shows only one phase of the circuit of a typical three-level NPC topology, for the three-level topology with three-phase NPCs, the other two phases have the same characteristic! like the circuit shown in Figure 1. In Figure 1, Si, S2, S3 and S4 are semiconductor components, FWDi, FWD2, FWD3 and FWD4 30 respectively connected in parallel with Si, S2, S3 and S4 are free-wheel diodes, Di and D2 are neutral point coupling diodes, capacitor Ci is for upper arm, C2 is capacitor for lower arm, P is a positive DC bus (direct current), N is a negative DC bus, NP is a 5 point bus neutral, and AC is an AC input / output bus (alternating current).
    As shown in Figure 1, such a three-tier NPC topology is characterized in that the voltage stress of each of the semiconductor components is reduced to half, compared to the two-tier topology, the number of semiconductor components contained in the unit power increases and its structure becomes more complicated, parasitic inductance in the power unit increases and can no longer be ignored. In particular, as the switching speed of ^, semiconductor components and power output are increasingly improved, parasitic inductance induces a high voltage when a semiconductor component is switched off under normal operation or short circuit, which can increase voltage stress when 20 semiconductor component, thereby reducing reliability and even damaging the semiconductor component. Therefore, it is significantly important to arrange power units properly in order to reduce stray inductance.
    Figures 2A-2C are circuit diagrams showing an example of a method for reducing the influence of a voltage induced by stray inductance on a semiconductor component in a conventional three-point neutral point topology.
    As shown in Figures 2A-2C, in the art, in order to reduce the influence of a voltage induced by the stray inductance on the topology of three NPC levels of semiconductor components, a conventional method adds a damping circuit (coupling circuit) connected in parallel with the semiconductor component, and the typical damping circuit is R, RC, RCD, and so on.
    When a semiconductor component Si is turned off, energy in the stray inductance is absorbed by an energy storage element in the damping circuit, and thus the voltage between the semiconductor component Si can be suppressed. Although this method can reduce the influence simply and effectively, when Si is turned on, energy absorbed by the damping circuit is released through Si, which leads to additional connection losses and deteriorates the dynamic performance of 15 semiconductor components. In addition, once additional high voltage devices are added, the drive has the disadvantages of an increased failure rate, reduced power density, improved cost, and so on.
    Currently, another method to reduce stray inductance is the laminated bus. The laminated bus has advantages of small parasitic inductance and effective suppression of EM1 (Electromagnetic Interference) and so on. Therefore, laminated busbars are widely applied to the high power frequency conversion field.
    In order to reduce stray inductance, the laminated bus must provide a path that makes currents through the respective layers of conductive parts to take mirror symmetry. The greater the symmetry, the smaller the area of the * current switching circuit in the conductive part, and • and the smaller the magnetic flux in the case of a constant flux density *, therefore, the less the stray inductance.
    Although parasitic inductance can be approximately ignored when laminated bus is used, some other problems still exist in these laminated buses in the art. For example, in particular on the three-level NPC circuit, as the number of components increases and the area of the components alone increases, multiple layers of laminated busbars are necessary to achieve the complicated electrical connection, and the cost of fabrication of such multiple layers of laminated busbars becomes high. In addition, as the number of busbars increases, parasitic inductance increases due to the increased thickness of the insulating layers located between the layers, and the insulation process between the layers becomes more complicated.
    For example, US Patent No. 6456516 Bl, entitled "Providing a three point low phase module inductor rail", describes a laminated bus structure. Laminated busbar proposed by this patent document is designed as three layers of laminated busbars, and can be extended to a topology of three NPC levels having N semiconductor switching components in series connection. Although parasitic inductance is reduced to some extent in this patent, the laminated bus in this patent is still a bus with multiple layers, and the corresponding thickness of insulating layers must be interposed between each two layers by an insulation process, which leads to the thickness of & * 'laminated busbar as a whole and causes a reduction in, parasitic inductance depending on the thickness of the layer: insulating. In addition, in the present patent, the shapes of the respective sub-buses are different from each other, and it is necessary to process bends and steps with different depths in the respective layers in order to connect each layer of bus with corresponding pins of the semiconductor components, the which makes the busbars manufacturing process complicated, and it is necessary to perform adhesion processing between the respective busbars in order to avoid spaces between the laminated layers due to the bending of the buses. Therefore, the electrical performance of such a bus structure is weak and: it counts against cost optimization. 1 'Likewise, another patent No. US 7881086 B2, entitled "Power conversion device and method for making the same" reveals a laminated bus structure. The laminate bus proposed by this US patent No. 7881086 B2 also comprises a multilayer bus (4. layers). Thus, there are problems such that the number of layers of busbars is too many to mitigate the effect of performing the low parasitic inductance, which is necessary to process different holes since the shapes of the respective sub25 busbars are different, from each other, and many laminated layers need more holes (more through holes). Therefore, the laminate bus proposed by this patent is also complicated and counts against cost optimization. ! • DISCLOSURE OF THE INVENTION
    To solve at least one of the problems mentioned above, an objective of the present patent application 'is to provide a laminated bus for use in a three-level NPC power converter, which effectively reduces stray inductance in the power converter, and it has a simple structure and is easy to install.
    To achieve the above objective, a first aspect of the present application is to provide a laminated bus for use in a three-level power converter NPC 10 proposed by the present application comprises: a first bus layer comprising a neutral point sub-bus configured for make electrical connections between the respective components in the converter and a neutral point potential, and a second 15 bus layer comprising a plurality of sub-buses configured to make electrical connections between respective components in the converter and a positive direct current (DC) input , a negative DC input, and an alternating current (AC) input / output on the converter, and between respective semiconductor switching components.
    A second aspect of the present patent application is to provide a three-level NPC power converter with low parasitic inductance, comprising: a group of semiconductor components comprising a group of upper arm components connected between a positive DC input and an input / AC output, and group of lower arm components connected between a negative DC input and the AC input / output, where the group of 30 upper arm components includes a first diode and • I coupling, a terminal from which it is connected to a neutral point potential located between the upper arm component group and the lower arm component group, and the lower arm component group comprises a second latching diode, a terminal of which is connected to the point potential neutral, a heat sink, in which the upper arm component group and the lower arm component group are mounted on, and a laminated busbar arranged on the group of semiconductor components, comprising: a first layer of. bus including a neutral point sub bus configured to make electrical connections between the first hitch diode, the second hitch diode and the neutral point potential, and a second bus layer including a plurality of sub bus bars configured to make connections electrical connections between the upper arm component group and the positive DC input, negative DC input, and the AC input / output, electrical connections between the lower arm component group and the negative DC bus, the AC input / output, and connections between the respective components in the upper arm component group and the lower arm component group, respectively.
    The present application can provide a mirror path for currents flowing through the switching step circuit. That is, the directions in which currents flow through an upper layer bus and a lower layer bus in the switching step are opposite each other, so that stray inductance in the power converter is effectively reduced, the voltage at the time the component is turned off is reduced, and the two layers of busbar structure are easy to obtain and install.
    These and other aspects of the present patent application 5 will be evident from the following description of the preferred modality made in conjunction with the following drawings, although variations and modifications here can be made without departing from the spirit and scope of the new concepts of the disclosure. BRIEF DESCRIPTION OF THE FIGURES
    The attached drawings illustrate one or more modalities of the application and, together with the written description, serves to explain the principles of the application. Whenever possible, the same reference numbers are used throughout the drawings to refer to the same or similar elements J i of the modalities, and where: Figure 1 is a circuit diagram showing a phase of the circuit of a topology of three levels of typical diode coupling ide;
    Figures 2A-2C are circuit diagrams showing an example of a method for reducing an influence of one; . voltage induced by parasitic inductance in a semiconductor i component in a conventional three-level NPC topology;
    Figures 3A-3D are circuit diagrams showing four switching circuits in one phase of a • power converter circuit having a three-level NPC topology during normal operation, respectively.
    Figure 4A is a schematic diagram showing a circuit of a power converter having a topology of three NPC levels according to a first embodiment of the present patent application,
    Figure 4B is a schematic diagram showing a distribution of components of the power converter having the topology of three NPC levels according to the first embodiment of the present patent application,
    Figure 5A is a schematic diagram showing the structure of each phase of the power unit in the power converter having the topology of three levels NPC according to the first embodiment of the present patent application,
    Figure 5B is a schematic diagram showing the structure of the laminated bus according to the first embodiment of the present patent application,
    Figure 5C is a schematic diagram showing the structure of an A6 sub-bus according to the first embodiment of the present patent application,
    Figure 6A is a schematic diagram showing a distribution of a switching circuit 1 on the laminated bus according to the first embodiment of the present patent application,
    Figure 6B is a schematic diagram showing a distribution of a switching circuit 2 on the laminated bus in accordance with the first embodiment of the present patent application, ''
    Figure 6C is a schematic diagram showing a distribution of a switching circuit 3 on the laminated bus according to the first embodiment of the present patent application,
    Figure 6D is a schematic diagram showing a distribution of a switching circuit 4 on the laminated bus according to the first embodiment of the present patent application, '
    Figure 7A is a schematic diagram 'showing the set of a power unit phase in the 5 power converter having the topology of three NPC levels according to the first embodiment of the present patent application,
    Figure 7B is an exploded schematic diagram showing the power unit assembly in Figure 7A,
    Figure 8A is a schematic diagram * showing a circuit of a power converter having a topology of three NPC levels according to a second embodiment of the present patent application,
    Figure 8B is a schematic diagram showing a distribution of components in the power converter having the topology of three NPC levels according to the second embodiment of the present patent application,
    Figure 9A is a schematic diagram showing the structure of each phase power unit in the power converter having the three-level NPC topology according to the second embodiment of the present patent application,
    Figure 9B is a schematic diagram 'showing the structure of the laminated bus according to the second embodiment of the present patent application,
    Figure 9C is a schematic diagram 'showing the structure of a sub-bus B6 according to the second embodiment of the present patent application,
    Figure 10A is a schematic diagram showing a distribution of a switching circuit 1 on the laminated bus in accordance with the second embodiment of the present patent application,
    Figure 10B is a schematic diagram showing a distribution of a switching circuit 2 on a laminated bus in accordance with the second embodiment of the present patent application,
    Figure 10C is a schematic diagram showing a distribution of a switching circuit 3 on the laminated bus in accordance with the second embodiment of the present patent application,
    Figure 10D is a schematic diagram showing a distribution of a switching circuit 4 on the laminated bus according to the second embodiment of the present patent application,.
    Figure 11A is a schematic diagram showing the power converter assembly having the topology of three NPC levels according to the second embodiment of the present patent application,
    Figure 11B is an exploded schematic diagram showing the power converter assembly in Figure 11A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
    Hereinafter, the modalities of the present patent application are described in detail. It should be noted that the modalities are illustrative only, and do not limit this application.
    The present application will now be described more fully below with reference to the accompanying drawings, in which exemplary modalities of the application are shown. This application can, however, be carried out in many different ways and should not be. interpreted as limited to the modalities established here. Instead, these modalities are provided for this description to be thorough and complete, and will fully convey the scope of application to those skilled in the art. Like reference numbers refer to like elements 5 throughout.
    The terminology used here is for the purpose of describing specific modalities only and is not intended to limit application. As used herein, the singular forms "one", "one" and "a" are intended to include the 10 plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", or "includes" and / or "including" or "has" and / or "having", when used herein, specify the presence of aspects, 15 regions, integers, steps, operations, elements and / or components established, but do not exclude the presence or addition of one or more aspects, regions, integers, steps, operations, elements, components and / or groups thereof.
    Unless otherwise defined, all terms 20 (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in dictionaries; commonly used, 25 should be interpreted as having a meaning that is consistent with its meaning in the context of the relevant art and the present description, and should not be interpreted in an idealized or excessively formal manner, unless expressly defined 30 here. * As used herein, the term "plurality" '. means a number greater than one.
    Figures 3A to 3D are circuit diagrams showing four switching circuits in one phase of the circuit of a power converter having a topology of three NPC levels, during normal operation, respectively.
    A switching circuit 1 is shown in Figure 3A. With reference to Figure 3A, switching circuit 1 flows from an upper arm bus capacitor Ci, semiconductor components Si, coupling diode D-_ and connectors between the above components, to an AC output terminal, as shown by the arrows in Figure 3A. Since the current flowing through Si is reduced and the current flowing through the latching diode Di is increased when Si transitions from an on to an off state, the voltage induced by the stray inductance can be applied through Si (the direction of the same is shown in Figure 3A) and, thus, the electrical stress for Sié increased.
    A switching circuit 2 is shown in Figure 3B.
    With reference to Figure 3B, switching circuit 2 flows from the AC terminal and through the upper arm bus capacitor Ci, free-wheel diodes FWDi and FWD2, semiconductor component S3, latching diode D2 and connectors between the above components referred to, as shown by the arrows in Figure 3B. Since the current flowing through S3 and D2 is reduced and the current flowing through the freewheeling diodes FWDi and FWD2 is increased when S3 transitions from the on to the off state, the voltage induced by the stray inductance can be applied across from S3 (the direction of which is shown in Figure 3B), and thus the stress stress for S3 is increased.
    A switching circuit 3 is shown in Figure 3C.
    With reference to Figure 3C, switching circuit 3 flows from the AC terminal and through a lower arm bus capacitor C2, semiconductor component S4, coupling diode D2 and connectors between the above components, as shown by the arrows in Figure 10 3C. Since the current flowing through S4 is reduced and the current flowing through the latching diode D2 is increased when S4 transitions from the on state to the off state, the voltage induced by the stray inductance can be applied through S4 (the direction of the same 15 is shown in Figure 3C), and thus, the electrical stress for S4 is increased.
    A switching circuit 4 is shown in Figure 3D. With reference to Figure 3D, the switching circuit 4 flows from the lower arm bus capacitor C2, component 20 semiconductor S2, free-wheel diodes FWD3 and FWD4, coupling di Di and connectors between the above components, to a terminal of AC output, as shown by the arrows in Figure 3D. Since the current flowing through S2 and the latching diode Di is reduced and the current flowing through FWD3 and FWD4 is increased when S2 transitions from the on to the off state, the voltage induced by the stray inductance can be applied through S2 (the direction of which is shown in Figure 3D), and thus the stress stress for S2 is increased.
    Therefore, in a three-level NPC power converter, in which the states of component change, the voltage induced by the stray inductance can increase the voltage stress for the semiconductor components, thus affecting performance and destroying them, improving requirement 5 for the performance of semiconductor components when manufacturing a power converter, and thus increasing the cost of manufacturing them. The above negative effects can be eliminated by reducing the parasitic inductance of the power converter.
    Therefore, the present patent application provides a laminated bus for an NPC three-level power converter, consisting of two bus layers, in which a bus layer comprises a neutral point sub bus configured to make electrical connection 15 between components of the three-level NPC power converter and a neutral point potential, and another bus layer can include a plurality of sub-buses, configured, respectively, to make electrical connections between the respective components in the three-level NPC power converter and one positive DC input, negative DC input, AC input / output and electrical connections between the respective components.
    In a laminated bus according to one embodiment of the present application, the main parts of the two 25 buses are located respectively in two different planes. Here, the main part of each bus layer refers to a bus conductor part of each bus layer, which will be described in detail later.
    The present application can provide a mirror path. for the current flowing through the circuit during *. switching step through the design of two busbar layers, that is, the directions of the currents that flow through the upper and lower busbar layers in the 5 switching phase assume mirror symmetry, thus the parasitic inductance in a power converter it can be reduced and voltage stress can be reduced when semiconductor components are turned off, and a two-layer bus structure can be achieved and installed easily.
    In comparison with the method in Figures 2A-2C, the present patent application does not increase the number of components, thus simplifying the manufacturing process, and the dynamic characteristics of the semiconductor components 15 may not be influenced. In addition, the failure rate and power density of the converter are not reduced and their cost is not increased since no additional components are added.
    In comparison with the laminated busbar proposed by 20 US Patent No. 6456516 Bl, in the case of the same voltage level, the same insulation material and the same insulation process, the operating voltage between the two bus layers according to The present patent application is half of a bus voltage, and such an arrangement requires only one layer of insulator, the thickness of which is half that of a three-layer arrangement of busbars. Therefore, parasitic inductance in the two bus layers in the present patent application is less than in three layers. Furthermore, the process of manufacturing 30 buses in the present application is simple, and its cost is low, since the shapes of the buses are similar '. each other and the busbars do not need specific processes, such as flexion, adhesion, and so on.
    Compared to the laminated busbar proposed by US patent No. 7881086 B2, in the case of the same voltage level, the same insulation material and the same insulation process, the number of busbar layers in the present patent application is significantly reduced, and also the number of insulating layers, so parasitic inductance is correspondingly reduced. In addition, the number of holes in the connection bars in laminates of the present application is reduced, thus the cost of manufacturing the bars is reduced.
    The laminated bus for the three-level NPC power converter according to the present application will be described by different modalities. [A first modality]
    As shown in Figure 4A, an upper arm in a 20-phase circuit of a power converter having a three-level NPC topology comprises semiconductor components Sn and S13, freewheeling diodes FWDn and FWD13, respectively, connected in parallel with Sn and S13, and a lower arm thereof comprises 25 semiconductor components Sn and Sn, free-wheel diodes FWDu and FWD; 6, respectively connected in parallel with S14 and Sn. A terminal of a coupling diode D12 is connected to Sn and S13 upper arm, and the other terminal of the same is connected to a neutral point potential. One terminal of a diode of 30 coupling Dn is connected to S14 and Sn of the lower arm, and the other terminal of the same is connected to the neutral point potential. A Cn0 upper arm bus capacitor is connected in series between a positive DC input and the neutral point potential, and a C120 lower arm bus capacitor is connected in series between a negative DC input and the neutral point potential. In Figure 4A, "P" indicates the positive DC input, "N" indicates the negative DC input, "NP" indicates the neutral point potential, and "AC" indicates the AC input / output.
    In this modality, according to the connection relationships between the respective components in the power converter, the components in the power converter constitute different semiconductor modules and, thus, a laminated bus structure can be correspondingly arranged according to these modules. For example, as shown in Figure 4A, Sn and FWDn connected in parallel with it constitute a semiconductor module 11; D12 constitutes a semiconductor module 12; S13 and FWD13 connected in parallel with it constitute a semiconductor module 13; Si4 and FWD14 connected in parallel with it constitute a semiconductor module 14, D15 constitutes a semiconductor module; Si6 and FWD16 connected in parallel with it constitute a switching component module 16.
    The plurality of semiconductor modules forms a group of power unit components (or called as a group of semiconductor components) 111 in the power converter. As shown in Figure 4B, the power unit device group 111 may comprise six switching component modules 11, 12, 13, 14, 15 and 16 located on the same plane, all of which are fixed to the same heatsink 10 .
    With reference to Figure 4B, in order to make the currents flowing through the laminated bus in the upper and lower layer, mirror symmetry in the 5 switching step, according to electrical connections between the respective components in the three-level NPC circuit topology , semiconductor modules 11, 12 and 13 are arranged on one side, and 14, 15 and 16 are arranged on the other side opposite to one side. In addition, preferably, module 10 is parallel to 14, module 12 is parallel to 15, and module 13 is parallel to 16.
    With reference to Figures 5A and 7A, in the power converter having the topology of three levels NPC according to this modality, a phase of the power unit 100 in the power converter is done as an example to illustrate the structure of the power unit . The power unit 100 mainly comprises a heatsink 10, a group of components 111 including the semiconductor component modules 11, 12, 13, 14, 15 and 16, and the sub-buses 20 Al, A2, A3, A4, A5 and A6, each of the sub-buses being divided into part of conductor and part of connector by function. In this modality, the respective sub-buses are, respectively, connected to the corresponding components in the power unit. Specifically, a 25 pin Cn of 11 is connected to a connection hole Cu 'of sub-bus Al, and connector 17 of sub-bus Al is used as the positive DC input terminal, which is connected to a bus of positive DC input through the upper arm capacitor Cn0. An Eu pin 11, a 30 K12 pin 12 and a C13 pin 13 are electrically connected to the connection holes Eu ', K12' and C13 'of sub-bus A2, respectively. An Ei3 pin of 13 and a Ci6 pin of 16 are electrically connected to connection holes Eis 'and Ci6' of sub-bus A5, respectively, and a connector 5 110 of sub-bus A5 is used as the input / output terminal B.C. An EI6 pin of 16, an A15 pin of 15 and a Ci4 pin of 14 are electrically connected to connection holes EiV, A15 'and Ci / of the A3 sub-bus, respectively. An Ei4 pin of 14 is electrically 10 connected to a connection hole Eu1 of sub-bus A4, and connector 18 of sub-bus A4 is used as a negative DC input terminal, which is connected to a common negative DC bus via lower arm capacitor C120. An A12 pin of 12 and a Ki5 pin of 15 are 15 electrically connected to the connection holes A12 'and K15' of the neutral point sub bus A6 disposed on the first layer, and the connector 19 of the neutral point sub bus A6 is used as a neutral point potential connection terminal in the one phase of the 20 power converter circuit, which is connected to the upper arm capacitor C110 and the lower arm capacitor Ci2o-
    In Figure 5B, on the AO laminated bus composed of sub-buses Al, A2, A3, A4, A5 and A6, connector 17 (that is, the connector of sub-bus Al) is connected to the positive DC input bus, connector 18 (that is, the A4 sub-bus connector) is connected to the negative DC input bus, connector 19 (that is, the A6 sub-bus connector) is connected to a neutral point potential bus, and connector 110 (that is, the connector of sub-bus A5) is connected to an AC input / output bus.
    In Figure 5B, in this embodiment, the laminated busbar AÓ is positioned on the group of components of power unit 111. The laminated busbar AO comprises two 5 layers of busbars. A first bus layer on the AO laminated bus is a neutral point sub bus A6, which is a one phase neutral bus potential of the power converter circuit having the NPC three-level topology, and includes connector 19 A second bus layer on the AO laminated bus comprises a plurality of sub-buses A1-A5, which make the electrical connection between the semiconductor modules and the positive DC bus, the negative DC bus and the AC input / output bus, the electrical connections between the semiconductor modules, and have the connector 17, 18 and 110. I
    Therefore, in this modality, the AO laminated bus comprises six sub-buses A1-A6. The present patent application has the sub-bus A6 as an example to illustrate the structure of each of the sub-buses in this modality.
    As shown in Figure 5C, the sub-bus A6 comprises a conductor A60 and a connector A61. Conductor A60 is a portion of sub-bus A6 that is used to provide a flow path for current through semiconductor modules, and connector A61 is used to connect conductor A60 with an external device, such as a semiconductor module. , capacitor, motor, cable or the like, in an effective connection way. Depending on different connection objects, connector A61 can comprise at least one connection terminal A610, connection hole A611, through hole A612 or the like. For example, connector A61 can be implemented as connector 19 in Figure 5A, and only connector 19 comprises connection terminals and connection holes. Likewise, in other sub-buses, the connector can be implemented as connector 17 and 18 in Figure 5A, and connector 17 and 18 also include only the connection terminals and connection holes.
    In the present application, if necessary, the bus connector can be implemented in several ways, for example, bending towards space, rivet, protrusion or concave, screw, buckle, and connection hole and through hole in various ways, and so on. According to an example of the present application, such as the connection of semiconductor modules through holes, each of the sub-buses in the laminated bus is drilled in the positions corresponding to the positions of the respective components in the semiconductor modules. The 20 holes can be classified into two types according to their diameters. A small hole having a smaller diameter is a connection hole, and each of the sub-buses is electrically connected to the corresponding terminal of the semiconductor modules through 25 respective connection holes. A large hole having a larger diameter is a through hole, and the through holes in each of the sub-buses are not electrically connected to the pins of the semiconductor modules. The drawings indicate just one example that 30 holes are round holes, but those skilled in the art should appreciate that the shapes of the holes are not "limited to this, and can be holes in various shapes, such as elliptical holes, square holes, and so on, while the holes can implement the 5 functions of the connection holes above or the through holes above and be distinguished from each other according to the two functions above ..
    The laminated busbar AO may further comprise a portion of insulating material. The insulating material portion is sandwiched between two sub-busbars with different operating voltages and stacked together. Here the laminated busbar AO as an example, an insulating layer exists between the upper and lower layer of busbars, and the insulating layer can be attached to a surface of the sub-bus A6, or can be attached to surfaces of the sub-buses Al, A2, A3, A4 and A5, or can be attached to the surfaces of sub-buses Al, A2, A3, A4, A5 and A6 simultaneously. The insulating layer may not be attached to any sub-busbar surface, but it is located independently between the two sub-busbar layers, and effective gripping between the upper and lower busbar layers is achieved by means of lamination, adhesion, and so on. As shown in Figures 5A and 5B, the neutral point A6 is arranged separately on the top of the laminated bus, and the operating voltages between the other sub-buses located in the second layer and the neutral point A6 are half of the entire operating voltage. Power converter DC. However, in the second bus layer, the operating voltages between a plurality of sub-bus, that is, between Al and A2, between A2 and A5, between A3 and A5, between A3 and A4, and between A2 and A3 are also half of the entire DC operating voltage of the converter and the operating voltage between Al and A4 is equal to the entire 5 DC operating voltage of the converter.
    In this mode, the laminated bus is arranged in two layers, which makes the currents flow through the upper and lower layer of busbars with substantially mirror symmetry, which effectively reduces stray inductance in the power converter, and further reduces voltage stress for switching components. In addition, the neutral point sub-bus arranged in one of the two layers can completely cover all the buses arranged in another layer, which further reduces the stray inductance in the power converter.
    Hereinafter, the influence of the laminated bus according to this modality on the stray inductance in a three-level NPC power converter will be described with reference to Figures 6A-6D.
    Figure 6A is a schematic diagram showing a distribution of a switching circuit 1 on the laminated bus according to a first embodiment of the present application. Figure 6B is a schematic diagram showing a distribution of a switching circuit 2 on the laminated bus according to the first embodiment of the present application. Figure 6C is a schematic diagram showing a distribution of a switching circuit 3 on the laminated bus according to the first embodiment of the present application. Figure 6D is a schematic diagram showing a f » distribution of a switching circuit 4 on the laminated 'bus' according to the first embodiment of the present application.
    With reference to Figure 3A and Figure 6A, at the moment 5 when semiconductor component Sn is switched off, switching circuit 1 flows through a sub-bus Al, semiconductor module 11, sub-bus A2 and semiconductor module 12 which are arranged in the first layer, and neutral point sub bus A6 that is, disposed in the second layer.
    Specifically, the current in switching circuit 1 flows through the Cuo-Cn-En-Kn-An-Cno route, that is, starting from the anode terminal of the upper arm bus capacitor Cno to the 11-way semiconductor module sub-bus Al and the Cu terminal of semiconductor module 15, still leading from another terminal Eu of semiconductor module 11, to semiconductor module 12 via sub-bus A2 and terminal K12 of semiconductor module 12, still leading from from another terminal A12 of the semiconductor module 12, and ending at the cathode terminal of the upper arm bus capacitor Cno via neutral point sub bus A6. Since A6 and Al, A2 are located in the different plane, and preferably A6 completely covers them, the switching circuit current path 1 is superimposed, and thus the generated stray inductance is very small. The more switching circuit 1 overlaps, the less parasitic inductance switching circuit 1 causes. ;
    With reference to Figure 3B and Figure 6B, at the moment when semiconductor component S13 is switched off, 30 switching circuit 2 flows through sub-bus Al, semiconductor module 11, sub-bus A2, semiconductor module 13, sub-bus A5, semiconductor module 16, sub-bus A3, semiconductor module and neutral bus sub-bus A6. Specifically, the current in the switching circuit.2 flows through the path C110-C11-E11-C13-E13-C16-E16-A15-K15-K15C110 that is, from the anode terminal of the upper arm bus capacitor Cno , for semiconductor module 11 via sub-bus Al and Cu terminal of semiconductor module 11, still taking ..from another terminal I of semiconductor module 11, for semiconductor module 13 via sub-bus A2 and terminal Ci3 of semiconductor modules 13, still taking from another terminal E13 of the semiconductor module 13, to the semiconductor module 16 by means of sub-busA5 and terminal Cie of semiconductor module 16, still leading from another terminal Eiβ of semiconductor module 16, to semiconductor module 15 via sub-bus A3 and AX5 terminal of semiconductor module 15, still leading from another terminal K15 of semiconductor component 15, and ending at the cathode terminal of the upper arm bus capacitor Cno via sub-bus A6. Since A6 and Al, A2, A5, 'A3 are located in different planes, and preferably A6 completely covers them, the current path of switching circuit 2 is superimposed, and thus' the parasitic inductance generated is too small. The more switching circuit 2 overlaps, the less parasitic inductance switching circuit 2 causes.
    With reference to Figure 3C and Figure 6C, at the moment when semiconductor component S14 is switched off, 30 switching circuit 3 flows through sub-bus A4, semiconductor module 14, sub-bus A3, semiconductor module 15 and point sub-bus neutral A6. Specifically, a. Current in the switching circuit 3 flows through the path of CI20-EI4-CI4-AI5-K15-CI20Z IE, from the 5 anode terminal of the lower arm bus capacitor C120, to the semiconductor module 15 via sub- neutral point bus point A6 and terminal K15 of semiconductor module 15, still leading from another terminal Ai5 of semiconductor module 15, to semiconductor module 14 via sub10 bus' A3 and terminal C14 of semiconductor module 14, still leading to starting from another terminal K14 of semiconductor module 14, and ending at the cathode terminal of the lower arm bus capacitor C120 via subbase A4. Since A6 and A3, A4 are located in 15 different planes, and preferably A6 covers them completely, the current path of the switching circuit 3 is superimposed, and thus the parasitic inductance generated is very small. The more switching circuit 3 overlaps, the less stray inductance 20 switching circuit 3 causes.
    With reference to Figure 3D and Figure 6D, at the moment when semiconductor component S12 is turned off, switching circuit 4 flows through sub-bus A4, semiconductor module 14, sub-bus A3, semiconductor module 16, 25 sub-bus A5, semiconductor module 13, sub bus A2, semiconductor module 12 and neutral point sub bus A6. Specifically, the current in the switching circuit 4 flows through the path of C120-A12-K12-C13-E13 C16-E16-C14-C120, that is, from the anode terminal of the lower arm capacitor Ci2o < for the module. semiconductor 12 via neutral point sub-bus A6 and ~ α terminal A12 of semiconductor module 12, still leading to another terminal K12 of semiconductor module 12, for semiconductor module 13 via sub-bus A2 and terminal C13 of semiconductor module 13 , still leading from another terminal E13 of semiconductor module 13, to semiconductor module 16 through sub-bus A5 and terminal C16 of semiconductor module 16, still leading from another terminal Eig of semiconductor module 16, to semiconductor module 14 through subbus A3 e. terminal Ci4 of semiconductor module 14, still leading from another terminal E14 of semiconductor module 14, and ending at the terminal 'of cathode of capacitor of bus: of lower arm C120 via sub-bus A4. Since A6 and A2, A5, A3, A4 are located in different planes, and preferably A6 covers them completely, the current path of switching circuit 4 is superimposed, and thus the parasitic inductance generated is very small. The more switching circuit 4 overlaps, the less stray inductance 20 causes switching circuit 4.
    As described above, the first embodiment of the present application provides a mirror path for currents in the switching step, in principle, reduces the switching circuit area and thus effectively reduces the stray inductance. In comparison with the various layers of laminated busbars, parasitic inductance in the present application can be reduced further. However, the laminated bus comprises only two layers and for the connections between the respective sub-bus in each of the two 30 layers and the semiconductor modules, it is not necessary to make a specific process and, therefore, the laminated bus according to this modality it has a structure that is simplified and easy to manufacture.
    As a modification of the first modality, the 5 positions of the semiconductor modules 11 and 14, the positions of the semiconductor module 12 and 15 and the positions of the semiconductor module 13 and 16 can be switched. Likewise, the positions of sub-bus A1 and A4 and the positions of sub-bus A2 and A3 are switched, and thus the decrease in parasitic inductance can also be achieved. According to the laminated bus described above, those skilled in the art should appreciate that the present application can be implemented in any other structure of the semiconductor modules 11-16 and the sub-buses, as long as this can make currents in the mirrored substantial laminated buses. .
    Hereinafter, a set of a power unit phase of the power converter having a three-level NPC topology according to this embodiment will be described 20 with reference to Figure 7A and Figure 7B.
    As shown in Figure 7A, the power unit 100 further comprises a group of capacitors 150 and a laminated bus DC 160. The 150 comprises an upper arm capacitor Cn0 and a lower arm capacitor Ci20. Since the voltages involved in the power converter are very high, the capacitors used in the present application are large, and it is preferable to supply the laminated bus DC 160 for the connection of the respective Cno terminals, C120 θ laminated bus A0. It should be noted that the present patent application is not limited to this, and the power converter of the present application can be achieved in other methods or without the laminated DC bus. '
    The structure of the power unit is as shown in Figure 7B. With reference to Figure 7B, A7 is a bus to connect the CHO upper arm capacitor, A8 is a bus to connect the lower arm capacitor C120 and A9 is a neutral point bus to connect the neutral point sub bus A6 to the laminated bus TO. The connection between connector 17 of AO and connector A70 of A7 is like a positive DC input. The connection between connector 18 of AO and connector A81 of A8 is like a negative DC input. The connection between connector 19 of AO and connector A92 of A9 is like a neutral point. The AC input / output bus connector part AC 110 is connected to the input / output device (for example, a filter or a motor). Meanwhile, connector A73 of A7 is connected to the 'upper arm capacitor busbars of other power unit phases in the power converter, the A83 connector A83 of A8 is connected to the lower arm capacitor busbars of other unit phases. power in the power converter, and the A9 connector of A93 is connected to the other natural point buses of other phases of power units in the power converter. [A second modality]
    As shown in Figure 8A, in this modality, S2n, S22U S222 and S232 are semiconductor components, FWD211, FWD221, FWD222 θ FWD232 are free wheel diodes, and FWD212 FWD231 are coupling diodes, C2io is an upper arm bus capacitor, and C22o is a lower arm bus capacitor. .
    The difference between the second modality and the first modality is that there are only three semiconductor modules. In this modality, the semiconductor components S2n, FWD211 and FWD2i2 constitute a semiconductor module 21, the semiconductor components S22i, FWD221, S222 and FWD222 constitute a semiconductor module 22, and the semiconductor components S232, FWD23i and FWD232 constitute a semiconductor module 23. A plurality of semiconductor modules 10 form a power unit component group 211.
    As shown in Figure 8B, the power unit component group 211 comprises semiconductor modules 21, 22 and 23, which are located on the same plane. All 15 semiconductor modules in 211 are attached to the same heatsink 20.
    In this modality, since the semiconductor components S2n, FWD211 and FWD2i2 are contained in the semiconductor module 21, S2n, FWD2n and FWD212 share a common 20 pin E2n / C2i2 connection. Likewise, the S22i, FWD22X and S222, FWD222 semiconductor components share a common E22I / C222 connection pin, and the S232, FWD23 semiconductor components and the FWD23X hitch diode share a common E23i / C232 connection pin.
    Therefore, as shown in Figure 8B, there are only three pins driven out of each of the semiconductor modules. For example, the pins driven from the semiconductor module 21 are E21i / C2i2, E2i2 and C2n, and other semiconductor modules are the same.
    With reference to Figures 9A and 11A, take a power unit phase 200 in the power converter as an example to illustrate the structure of the power converter according to this modality. The power unit 200 comprises mainly a heatsink 20, a group of power unit components 211, including semiconductor modules 21, 22 and 23, and subbuses Bl, B2, B3, B4, B5 and B6, each one of the sub-buses being divided into part of conductor and part of connector by function. In this mode, the respective sub-buses 10 are connected to the components in the power unit, respectively. Specifically, on the laminated bus B0 according to this modality, a pin C2n of the conductor module 21 is electrically connected to a connection hole C211 of the sub-bus Bl, and a connector 27 of the sub-bus Bl is used as a DC input terminal positive, which is connected to a positive DC input bus via an upper arm capacitor C2io An E2II / C212 pin from the semiconductor module 21 and a C22i pin from the semiconductor module 22 are electrically connected to the E2n / C212 connection holes 'of sub-bus B2, respectively. A pin E222 of the semiconductor module 22 and a pin E23i / C232 of the semiconductor module 23 are electrically connected to the connection holes £ 222'1 £ 231 '/ C232' of the sub-bus B3, respectively. An E232 pin from semiconductor module 25 is electrically connected to a connection hole E232 'of sub-bus B4, and a connector 28 of sub-bus B4 is used as a negative DC input terminal, which is connected to a bus negative DC input through a lower arm capacitor C22oA 30 pin E221 / C222 of semiconductor module 22 is electrically connected to a connection hole E221 '/ C222' of sub-bus B5, and a connector 210 of sub-bus B5 is used as an AC input / output terminal. A pin E2I2 of the semiconductor module 21 and a pin C23i of the semiconductor module 5 are electrically connected to the connection holes E2I2 'and C23 / of the neutral point sub bus B6, respectively, and a connector 29 of the neutral point sub bus B6 is used as a neutral point connection terminal, which is connected to the upper arm capacitor C210, and the lower arm capacitor C220.
    Figure 9B, the connector 27 of the laminated bus B0 composed of sub-buses Bl, B2, B3, B4, B5 and B6 (that is, the connector of the sub-bus Bl) is connected to a positive DC input bus of the converter power, 15 connector 28 (ie, sub-bus connector B4) is connected to a negative DC input bus of the power converter, connector 29 (ie, sub-bus connector B6) is connected to a neutral point potential bus of the power converter, and connector 210 20 (that is, the sub bus connector B5) is connected to an AC input / output bus. As shown in Figure 9B, in this embodiment, the laminated bus B0 is arranged over the group of power unit components 211. The laminated bus 25 B0 comprises two layers. The first layer is a neutral point sub-bus B6, which is a neutral point potential bus of an NPC three-level topology phase with connector 29. The second layer comprises a plurality of sub-buses B1-B5, which is configured to make electrical connections between the ■ S 'semiconductor modules and the positive DC input bus, the negative DC input bus, the AC input / output bus and electrical connections between the respective semiconductor modules with connector 27, 28 and 210.
    Therefore, in this mode, the laminated bus B0 comprises six sub-buses B1-B6. With reference to Figure 9C, this modality has the sub-bus B6, as, for example, to explain the structure of each one. As shown in Figure 9C, sub-bus B6 comprises conductor part B60 and connector part B61. B60 is used to provide a flow path for the current in the switching component modules. B61 is used to connect B60 to an external device, such as semiconductor component module, capacitor, motor, cable or the like, in an effective connection manner. Depending on different connection objects, B61 can comprise at least one of connection terminals B610, connection holes B611, and through holes B612, and so on. For example, B61 can be implemented as connector 29 in Figure 9A, and connector 29 only comprises connection terminals and connection holes. Likewise, in other sub-buses, the connector can be implemented as connector 27 and 28 in Figure 9A, and connector 27 and 28 also includes connection terminals and connection holes.
    In the present application, if necessary, the connector part can be implemented in several ways, for example, bending towards space, rivet, protrusion or concave, screw, buckle, and connection hole and through hole in various forms, and so on. According to an example of the present application, such as the ■ connection of semiconductor modules through holes, each sub-bus in the laminated bus is drilled in the positions corresponding to the positions of the respective components in the semiconductor modules. The 5 holes can be classified into two types according to the diameter of the hole. A small hole having a smaller diameter is a connection hole, and each of the subbars is electrically connected to the corresponding pins of the semiconductor modules through 10 respective connection holes. A large hole having a larger diameter is a through hole, and the through holes in each of the sub-buses are not electrically connected to the pins of semiconductor modules. The drawings indicate just one example that 15 holes are round holes, but those skilled in the art should appreciate that the shape of the hole is not limited to this, and the hole can be in various forms, such as ellipse hole, square hole, and so on, while the orifice can implement the functions of the above connection orifice 20 or the through-hole above and be distinguished from each other according to the two functions above.
    The laminated bus B0 further comprises a portion of insulating material. The portion of insulating material is placed between the two sub-busbars with different operating voltages and stacked together. Here the laminated bus B0, as an example, an insulating layer exists between the upper and lower layer of busbars, and the insulating layer can be attached to a surface of the sub-bus B6, or it can be attached to the surfaces of the sub-buses Bl, B2 , B3, B4 is B5, or can be attached to the surfaces of the sub-buses Bl, B2, B3, B4, B5 and B6 simultaneously. The insulating layer may not be attached to any surface of the sub-busbars, but is located independently between the two layers of sub-busbars, and the effective gripping between the upper and lower layer of busbars is achieved through lamination, adhesion and so on. As shown in Figure 9A and Figure 9B, the neutral point sub bus B6 10 is arranged separately at the top of the laminated bus, and the operating voltages between the other sub buses in the second layer and the neutral point sub bus B6 are half the entire DC operating voltage of the power converter. However, in the second 15-bus layer, the insulation voltages between a plurality of sub-bus, that is, between sub-bus Bl and sub-bus B2, between sub-bus B2 and sub-bus B3, between sub-bus B3 and sub-bus B5, between sub-bus B2 and sub-bus B5, account for half of the entire DC operating voltage.
    In this mode, the laminated bus is arranged in two bus layers, which causes currents to flow through the upper and lower bus layers of substantially mirror symmetry, which effectively reduces parasitic inductance in the power converter, and further reduces voltage stress to semiconductor components. In addition, the neutral point sub-bus arranged in one of the two layers can completely cover all the buses arranged in another layer, which further reduces the stray inductance in the power converter. '' Hereinafter, the influence of the laminated bus in accordance with this modality of parasitic inductance in a three-level NPC power converter will be described with reference to Figures 10A-10D.
    Figure 10A is a schematic diagram showing a distribution of a switching circuit 1 on the laminated bus in accordance with the second embodiment of the present application. Figure 10B is a schematic diagram showing a distribution of a switching circuit 2 on a laminated bus according to the second embodiment of the present application. Figure 10C is a schematic diagram showing a distribution of a switching circuit 3 of the laminated bus in accordance with the second embodiment of the present application. Figure 10D is a schematic diagram showing a distribution of a switching circuit 4 on the laminated bus in accordance with the second embodiment of the present application. ■ With reference to Figure 3A and Figure 10A, at the moment when semiconductor component S211 is switched off, switching circuit 1 flows through a sub-bus Bl, within semiconductor module 21, and neutral point sub-bus B6. Specifically, the current in switching circuit 1 flows through the Caio-Caii-Caio-Eaiar path, that is, 25 starting from the anode terminal of the upper arm bus capacitor C210, to terminal CZ11 of semiconductor module 21 through the sub -Bl bus, still leading from terminal E212 of semiconductor module 21, terminating at the cathode terminal of the upper arm bus capacitor C210, that is, the lower arm bus capacitor anode terminal C220, via sub bus B6 . Since B6 and Bl are located in different planes, and preferably B6 completely covers Bl, the switching circuit current path 1 is superimposed, and thus the generated stray inductance is very small. The more switching circuit 1 overlaps, the less parasitic inductance switching circuit 1 causes.
    With reference to Figure 3B and Figure 10B, at the moment at which semiconductor component S222 is turned off, switching circuit 2 flows through sub-bus Bl, semiconductor module 21, sub-bus B2, semiconductor module 22, sub-bus B3, semiconductor module 23, and neutral point sub-bus B6. Specifically, the current in switching circuit 15 flows through the path of C2io_C2ii-E2ii / 2i2C221-E222-E231 / C232-C231-C210, that is, starting from the anode terminal of the upper arm bus capacitor C, to terminal C2n of semiconductor module 21 via sub-bus Bl, still leading from terminal E2n / 20 C212 of semiconductor module 21, to terminal C232 of semiconductor module 22 via sub-bus B2, still leading from terminal E222 of module semiconductor 22, for terminal E231 / C232 of semiconductor module 23 via sub-bus B3, still leading from terminal C231 of 25 semiconductor module 23, and ending at the cathode terminal of the upper arm bus capacitor C2io via sub-bus B6. Since B6 and Bl, B2 and B3 are in different planes, B6 preferably covers them completely, switching circuit current path 2 is superimposed, and thus the parasitic inductance generated is very small. The more switching circuit 2 overlaps, the less parasitic inductance switching circuit 2 causes.
    With reference to Figure 3C and Figure 10C, at the moment when semiconductor component S232 is switched off, 5 switching circuit 3 flows through sub-bus B4, semiconductor module 23 and neutral point sub-bus B6. Specifically, the current in the switching circuit 3 flows through the path of C22o-C23i-E232-C22O, that is, starting from the anode terminal of the lower arm capacitor C22or. To the C231 terminal of the semiconductor module 23, through the neutral point sub-bus B6, still leading from terminal E232 of semiconductor module 23, and ending at the cathode terminal of the lower arm bus capacitor C220 via sub-bus B4. Since B4 and B6 are located in different planes, and preferably B6 completely covers B4, the current path of the switching circuit 3 is superimposed, and thus the parasitic inductance generated is very small. The more the switching circuit 3 overlaps, the less stray inductance 20 the switching circuit 3 causes.
    With reference to Figure 3D and Figure 10D, at the moment when semiconductor component S22i is switched off, switching circuit 4 flows through sub-bus B4, semiconductor module 23, sub-bus B3, semiconductor module 22, 25 sub-bus B2, semiconductor module 21 and neutral point sub-bus B6. Specifically, the current in switching circuit 4 flows through the path of C22o-E2i2-E2n / C2i2C22i — E222 — E23I / C232 — E232 — C220, that is, from the lower arm bus capacitor anode C22o, to 30 terminal E2I2 of semiconductor module 21 via neutral point sub bus B6, still leading from terminal E211 / C212 of semiconductor module 21, to terminal C221 of semiconductor module 22 via sub bus B2, still leading from terminal E222 of semiconductor module 22, for 5 terminal E231 / C232 of semiconductor module 23 via sub-bus B3, still leading from terminal E232 • of semiconductor module 23, and ending at the cathode terminal of the lower arm bus capacitor C22O via sub-bus B4. Since B6 and B2, B3, B4 are located 10 in different planes, and B6 preferably covers them completely, the current path of the switching circuit 4 is superimposed, and thus the generated stray inductance is very small. The more switching circuit 4 overlaps, the less stray inductance switching circuit 4 15 causes.
    As described above, the second embodiment of the present application provides a mirror path for currents in the switching step, in principle, reduces the switching circuit area and thus effectively reduces the stray inductance. In comparison with the various layers of laminated busbars, parasitic inductance in the present application can be reduced further. Meanwhile, the laminated bus arrangement comprises only two layers, and for the connections between the respective sub-bus in each of the two layers and the semiconductor modules, it is not necessary to do a specific process and thus the laminated bus of According to this modality, it has a structure that is simplified and easy to manufacture.
    Hereinafter, a power converter assembly 30 having a topology of three NPC levels according to this embodiment will be described with reference to Figure 11A and Figure 11B.
    Unlike the first modality, in this modality take a three-phase circuit from the 5-power converter as an example to illustrate the entire electrical set. As shown in Figure 11A, the entire three-phase power unit assembly of the power converter comprises respective P210, 10 P220 and P230 phase power units implemented by this modality, heat sink P240, capacitor device group P250 and laminated DC P260 bus. Here, similar to the first modality, the power converter in this modality preferably provides DC laminated bus P260 to connect the respective bus connection parts of upper arm capacitor C2io, lower arm capacitor C220 θ laminated bus BO. It should be noted that the present patent application is not limited to this, and the power converter of the present application can be implemented in another way or without the laminated DC bus. '
    The structure of the power converter according to this modality is shown in Figure 11B. With reference to Figure 11B, upper arm bus capacitor C210 θ 25 lower arm bus capacitor C220 are arranged opposite. The power units P210, P220 and P230 are implemented in the form of the power unit described in the second modality of the present application. B24 is an upper arm bus capacitor, B25 is a 30 lower arm bus capacitor, and B26 is a neutral point bus. The connector B210 of P210, connector B220 of ’P220 and connector B230 of. P230 are respectively connected to the B240 connector of the upper arm bus capacitor B24, so as to be used as a positive DC 5 input, and B24 is connected to the upper arm capacitor C2io through a connection hole in it. The connector B21J of P210, connector B221 of P220, and. Connector B231 of P230 are respectively connected to the negative DC input of the. lower arm bus capacitor B25, so as to be 10. used as negative DC input, and B25 is connected to the lower arm capacitor .C220 via connection holes in it. Connector B212 of P210, connector B222 of P220 and connector B232 of P230 are respectively connected to the connector B260 of the bus.of neutral point B26, so that it can be used as a neutral point. Connector B213 from P210, connector B223 from P220, connector B233. P230 are respectively connected to the input / output device (eg motor), so that it can be used1 as an AC input / output terminal. .
    The laminated bus and the power converter with the laminated bus according to the present patent application have been described by the first modality and the second 'modality. ■ For those skilled in the art, the previous description of the exemplary modalities of the application was presented only for purposes of illustration and description and is not intended to be exhaustive or limit application to the precise forms revealed. Many modifications and variations are possible in light of the above teachings. Therefore, like the power conversion part of a variable frequency converter, the power converter can employ the structure of the laminated bus described in the modality and can also use the structure of the laminated bus modified in the modality.
    In addition, since the variable frequency converter is mainly composed of rectifier (conversion from alternating current to direct current), filter, inverter (conversion from direct current to alternating current, control unit, drive unit, detection unit and microprocessing unit, those skilled in the art can understand that the present application can be extended to any variable frequency converter having the laminated bus structure above.
    The modalities have been chosen and described 'in order to explain the principles of the application and its practical application, in order to enable other experts in the art to use the application and various modalities and with various modifications that are suitable for the particular intended use. Alternative modalities will be evident to specialists in the technique to which the present application refers without departing from its spirit and scope. Therefore, ■ the scope of the present patent application is defined by the appended claims instead of the previous description and the exemplary modalities described herein. '
    权利要求:
    Claims (8)
    [0001]
    1. Laminated bus (A0) for use in a three-level NPC power converter, comprising: a first bus layer comprising a neutral point sub-bus (A6), configured to make electrical connections between respective components in the power converter three-level NPC and a neutral point potential (NP), and a second bus layer comprising a plurality of sub-buses (A1-A5), configured to make electrical connections between the respective components in the three-level NPC power converter and a positive DC input (P), a negative DC input (N) and an AC input / output (AC) on the three-level power converter NPC and electrical connections between the respective components, where, the three-power converter NPC levels comprise: a first semiconductor module (11) comprising a first semiconductor component (S11) located on an upper arm of the three-level NPC power converter and a first diode free-wheel (FWD11) connected in parallel with the first semiconductor component (S11), a second semiconductor module (13) comprising a second semiconductor component (S13) located on an upper arm of the three-level NPC power converter and a second diode free-wheel (FWD13) connected in parallel with the second semiconductor component (S13), a third semiconductor module (16) comprising a third semiconductor component (S16) located on a lower arm of the three-level NPC power converter and a third diode free-wheel (FWD16) connected in parallel with the third semiconductor component (S16), a fourth semiconductor module (14) comprising a fourth semiconductor component (S14) located on a lower arm of the three-level NPC power converter and fourth diode freewheel (FWD14) connected in parallel with the fourth semiconductor component (S14), a fifth semiconductor module (12) comprising a first coupling diode (D12), a t terminal of which is connected between the first semiconductor module (11) and the second semiconductor module (13), and another terminal from which it is connected to the neutral point potential (NP) of the three-level power converter NPC, and a sixth semiconductor module (15) comprising a second latching diode (D15), a terminal from which it is connected between the third semiconductor module (16) and the fourth semiconductor module (14), and another terminal from which it is connected to the point potential neutral (NP) of the three-level NPC power converter, characterized by the fact that the second bus layer comprises: a first sub-bus (A1) configured to make an electrical connection between the first semiconductor module (11) and the DC input positive (P), a second sub-bus (A2) configured to make electrical connections between the first semiconductor module (11), the second semiconductor module (13) and the fifth semiconductor module (12), a third sub-bus (A3 ) configured to do electrical connections between the third semiconductor module (16), the fourth semiconductor module (14) and the sixth semiconductor module (15); a fourth sub-bus (A4) configured to make an electrical connection between the fourth semiconductor module (14) and the negative DC input (N), and a fifth sub-bus (A5) configured to make electrical connections between the second semiconductor module ( 13), the third semiconductor module (16) and the AC input / output (AC), and where the neutral point sub-bus (A6) is connected, respectively, to another terminal of the first coupling diode (D12) and another terminal of the second engaging diode (D15).
    [0002]
    2. Laminated bus (B0) for use in a three-level NPC power converter, comprising: a first bus layer comprising a neutral point sub-bus (B6), configured to make electrical connections between respective components in the power converter three-level NPC and a neutral point potential (NP), and a second bus layer comprising a plurality of sub-buses (B1-B5), configured to make electrical connections between the respective components in the three-level NPC power converter and a positive DC input (P), a negative DC input (N) and an AC input / output (AC) on the three-level power converter NPC and electrical connections between the respective components, where, the three-power converter NPC levels comprise: a first semiconductor module (21) comprising a first semiconductor component (S211) and a first coupling diode (FWD212) located on an upper arm of the power converter three-level NPC, a second semiconductor module (22) comprising a second semiconductor component (S221) located on the upper arm of the three-level NPC power converter and a third semiconductor component (S222) located on a lower arm of the power converter three NPC levels, and a third semiconductor module (23) comprising a fourth semiconductor component (S232) and a second hitch diode (FWD231) located on the lower arm of the three-level NPC power converter, where a terminal on the first coupling (FWD212) is connected between the first semiconductor component (S211) and the second semiconductor component (S221), and another terminal of the same is connected to a neutral point potential (NP) of the three-level NPC power converter, characterized due to the fact that the second bus layer comprises: a first sub-bus (B1) configured to make an electrical connection between the first semiconductor module (21) and the DC input p ositive (P), a second sub-bus (B2) configured to make an electrical connection between the first semiconductor module (21) and the second semiconductor module (22), a third sub-bus (B3) configured to make an electrical connection between the second semiconductor module (22) and the third semiconductor module (23); a fourth sub-bus (B4) configured to make an electrical connection between the third semiconductor module (23) and the negative DC input (N), and a fifth sub-bus (B5) configured to make an electrical connection between the second semiconductor module ( 22) and the AC input / output (AC), and where the neutral point sub-bus (B6) is connected, respectively, to the other terminal of the first coupling diode (FWD212) and another terminal of the second coupling diode (FWD231).
    [0003]
    3. Three-level NPC power converter with low parasitic inductance, comprising: a group of semiconductor components comprising a group of upper arm components connected between a positive DC input (P) and an AC input / output (AC) and a group of lower arm components connected between a negative DC input (N) and the AC input / output (AC), where the group of upper arm components further comprises a first coupling diode (D12), a terminal of which is connected to a neutral point potential (NP) located between the upper arm component group and the lower arm component group, and the lower arm component group further comprises a second latching diode (D15), a terminal of the which is connected to the neutral point potential (NP), a heat sink (10), in which the upper arm component group and the lower arm component group are assembled, and a laminated bus (A0), arranged on the group of c semiconductor components, and comprising: a first bus layer comprising a neutral point sub bus (A6) configured to make electrical connections between the first engaging diode (D12), the second engaging diode (D15) and the point potential neutral (NP), and a second bus layer comprising a plurality of sub-buses (A1-A5), configured to make electrical connections between the group of upper arm components and the positive DC input (P) and the input / output AC (AC), the electrical connections between the lower arm component group and the negative DC input (N) and the AC (AC) input / output, and electrical connections between the respective components in the upper arm component group and the group of lower arm components, respectively, characterized by the fact that the group of upper arm components further comprises: a first semiconductor module (11), comprising the first semiconductor component (S11) and the first r freewheeling diode (FWD11) connected in parallel with the first semiconductor component (S11), a second semiconductor module (13) comprising the second semiconductor component (S13) and the second freewheeling diode (FWD13) connected in parallel with the second semiconductor component (S13), the group of lower arm components further comprises: a third semiconductor module (16) comprising the third semiconductor component (S16) and the third freewheeling diode (FWD16) connected in parallel with the third semiconductor component (S16); a fourth semiconductor module (14) comprising the fourth semiconductor component (S14) and the fourth freewheeling diode (FWD14) connected in parallel with the fourth semiconductor component (S14), and the second bus layer comprising: a first sub-bus (A1) configured to make an electrical connection between the first semiconductor module (11) and the positive DC input (P); a second sub-bus (A2) configured to make electrical connections between the first semiconductor module (11), the second semiconductor module (13) and the first coupling diode (D12), a third sub-bus (A3) configured to make electrical connections between the third semiconductor module (16), the fourth semiconductor module (14) and the second coupling diode (D15), a fourth sub-bus (A4) configured to make an electrical connection between the fourth semiconductor module (14) and the negative DC input (N), and a fifth sub-bus (A5) configured to make electrical connections between the second semiconductor module (13), the third semiconductor module (16) and the AC input / output (AC).
    [0004]
    4. Power converter according to claim 3, characterized by the fact that the first bus layer is located on the second layer and the first bus layer completely covers all sub-buses in the second layer.
    [0005]
    5. Power converter according to claim 3, characterized by the fact that each of the sub-buses in the first sub-bus layer and the second sub-bus layer comprises, a conductor part as a main part, a connector part and an insulating material part, where each sub-bus is electrically connected to the corresponding semiconductor module, a common DC input, a neutral point bus and an AC (AC) input / output of a three-level circuit of the three-level power converter NPC via the bus connection part thereof, respectively.
    [0006]
    6. Three-level NPC power converter with low parasitic inductance, comprising a group of semiconductor components comprising a group of upper arm components connected between a positive DC input (P) and an AC input / output (AC) and a group of lower arm components connected between a negative DC input (N) and the AC input / output (AC), where the group of upper arm components further comprises a first coupling diode (FWD212), a terminal from which it is connected to a neutral point potential (NP) located between the group of upper arm components and the group of lower arm components, and the group of lower arm components further comprises a second engaging diode (FWD231), a terminal of which it is connected to the neutral point potential (NP), a heat sink (20), in which the group of upper arm components and the group of lower arm components are assembled, and a laminated bus (B0), arranged on the group semiconductor components, and comprising: a first bus layer comprising a neutral point sub-bus (B6) configured to make electrical connections between the first coupling diode (FWD212), the second coupling diode (FWD231) and the potential for neutral point (NP), and a second bus layer comprising a plurality of sub-buses (B1-B5), configured to make electrical connections between the group of upper arm components and the positive DC input (P) and the input / AC outlet (AC), the electrical connections between the lower arm component group and the negative DC input (N) and the AC (AC) input / output, and electrical connections between the respective components in the upper arm component group and the group of lower arm components, respectively, characterized by the fact that, the group of upper arm components further comprises a first semiconductor component (S211) and a second semiconductor component (S221), eog The lower arm component group further comprises a third semiconductor component (S222) and a fourth semiconductor component (S232), wherein the first semiconductor component (S211) and the first coupling diode (FWD212) constitute a first semiconductor module (21) , the second semiconductor component (S221) and the third semiconductor component (S222) constitute a second semiconductor module (22), and the fourth semiconductor component (S232) and the second coupling diode (FWD231) constitute a third semiconductor module (23) , and the second bus layer further comprises: a first sub-bus (B1) configured to make an electrical connection between the first semiconductor module (21) and the positive DC input (P), a second sub-bus (B2) configured for make an electrical connection between the first semiconductor module (21) and the second semiconductor module (22), a third sub-bus (B3) configured to make an electrical connection between the second semiconductor module (22) and the third semiconductor module (23); a fourth sub-bus (B4) configured to make an electrical connection between the third semiconductor module (23) and the negative DC input (N), and a fifth sub-bus (B5) configured to make an electrical connection between the second semiconductor module ( 22) and the AC (AC) input / output.
    [0007]
    7. Power converter according to claim 6, characterized by the fact that the first bus layer is located on the second layer and the first bus layer completely covers all sub-buses in the second layer.
    [0008]
    8. Power converter according to claim 6, characterized by the fact that each of the sub-buses in the first sub-bus layer and the second sub-bus layer comprises, a conductor part as a main part, a connector part and an insulating material part, where each sub-bus is electrically connected to the corresponding semiconductor module, a common DC input, a neutral point bus and an AC (AC) input / output of a three-circuit levels of the three-level NPC power converter via the bus connection part thereof, respectively.
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    同族专利:
    公开号 | 公开日
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    RU2546979C1|2015-04-10|
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    CN102882385B|2015-09-23|
    RU2013144660A|2015-04-20|
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    法律状态:
    2017-09-19| B03A| Publication of a patent application or of a certificate of addition of invention [chapter 3.1 patent gazette]|
    2018-02-20| B25G| Requested change of headquarter approved|Owner name: DELTA ELECTRONICS, INC. (CN) |
    2018-11-21| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|
    2020-01-21| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2020-06-02| B06A| Notification to applicant to reply to the report for non-patentability or inadequacy of the application [chapter 6.1 patent gazette]|
    2020-09-24| B09A| Decision: intention to grant|
    2020-12-29| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 22/10/2013, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    CN201210403971.1A|CN102882385B|2012-10-22|2012-10-22|For laminated bus bar structure and the power inverter of three level power converter|
    CN201210403971.1|2012-10-22|
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